The nanodamascene process: a versatile fabrication technique for nanoelectronic applications - Archive ouverte HAL
Communication Dans Un Congrès Année : 2015

The nanodamascene process: a versatile fabrication technique for nanoelectronic applications

G. Droulers
  • Fonction : Auteur
Marina Labalette
  • Fonction : Auteur
B. Sang
  • Fonction : Auteur
J. Richard
M. Pioro-Ladriere
  • Fonction : Auteur
S. Ecoffey
Abdelkader Souifi

Résumé

In this paper we present a versatile nanodamascene fabrication process for the realization of low power nanoelectronic devices. This process has been exploited for the fabrication of metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar nanometric resistive memories. Due to its low thermal budget, and materials, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.
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Dates et versions

hal-01489607 , version 1 (14-03-2017)

Identifiants

  • HAL Id : hal-01489607 , version 1

Citer

D. Drouin, G. Droulers, Marina Labalette, B. Sang, P. Harvey-Collard, et al.. The nanodamascene process: a versatile fabrication technique for nanoelectronic applications. IEEE NANO 2015 15th INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY, 2015, ROME, Italy. ⟨hal-01489607⟩
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