Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel, circuit technology has also considerably evolved. One example is Field Programmable Gate Arrays (FPGAs) that are now suitable for implementing the physical layer of most complex wireless communication systems. This has been made possible thanks to their high level of performance, flexibility, and bit-level programming. In these devices, the Dynamic Partial Reconfiguration (DPR) constitutes a well known technique for reconfiguring only a specific area within the circuit. This technique offers efficient resource utilization, reduced power consumption and permits the optimization of the configuration time. In our work, we benefit from this technology to implement a wireless communication system in hardware. Hardware reconfiguration is performed automatically according to adaptive decision processes running on top of a micro-kernel that manages partial reconfiguration. The system is implemented on a ZedBoard which features a Xilinx Zynq 7000 System on Chip (SoC).