Radiation Experiments on a 28nm Single-Chip Many-core Processor and SEU error-rate prediction
Résumé
This work evaluates the SEE static and dynamic sensitivity
of a single-chip many-core processor having implemented
16 compute clusters, each one with 16 processing cores. The SEU
error-rate of an application implemented in the device is predicted
by combining experimental results with those issued from
fault injection campaigns applying the CEU (Code Emulating
Upsets) approach. In addition, a comparison of the dynamic tests
when processing-cores cache memories are enabled and disabled
is presented. The experiments were validated through radiation
ground testing performed with 14 MeV neutrons on the MPPA-
256 many-core processor manufactured in TSMC CMOS 28HP
technology. An analysis of the erroneous results in processor
GPRs was carried-out in order to explain their possible causes.
