F. Bellard, QEMU, a Fast and Portable Dynamic Translator, USENIX ATC, FREENIX Track, pp.41-46, 2005.

K. Ebcio?-glu and E. R. Altman, DAISY: Dynamic Compilation for 100% Architectural Compatibility, ISCA, 1997.

J. C. Dehnert, B. K. Grant, J. P. Banning, R. Johnson, T. Kistler et al., The Transmeta Code Morphing/spl trade/ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges, International Symposium on Code Generation and Optimization, 2003. CGO 2003., 2003.
DOI : 10.1109/CGO.2003.1191529

D. Boggs, G. Brown, N. Tuck, and K. Venkatraman, Denver: Nvidia's First 64-bit ARM Processor, IEEE Micro, vol.35, issue.2, 2015.
DOI : 10.1109/MM.2015.12

S. Hu and J. E. Smith, Reducing Startup Time in Co-Designed Virtual Machines, ISCA, 2006.
DOI : 10.1145/1150019.1136510

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.75.9900

M. Paleczny, C. Vick, and C. Click, The Java HotSpot Server Compiler, JVM Research and Technology Symposium, 2001.

J. A. Fisher, P. Faraboschi, and C. Young, Embedded computing: a VLIW Approach to Architecture, Compilers and Tools, 2005.

T. Bollaert, Catapult Synthesis: A Practical Introduction to Interactive C Synthesis, High-Level Synthesis: From Algorithm to Digital Circuit, 2008.
DOI : 10.1007/978-1-4020-8588-8_3

C. Lee, M. Potkonjak, and W. H. Mangione-smith, MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, MICRO, 1997.

H. Kim and J. E. Smith, Dynamic Binary Translation for Accumulator-Oriented Architectures, CGO, 2003.

L. Baraz, T. Devor, O. Etzion, S. Goldenberg, A. Skaletsky et al., IA-32 execution layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium/spl reg/-based systems, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), 2003.
DOI : 10.1109/MICRO.2003.1253195

Y. Wu, S. Hu, E. Borin, and C. Wang, A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing, International Symposium on Code Generation and Optimization (CGO 2011), 2011.
DOI : 10.1109/CGO.2011.5764691

B. Dupont-de-dinechin, Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors, Euro-Par Parallel Processing, 2008.
DOI : 10.1007/978-3-540-85451-7_40

G. Agosta, S. Crespi-reghizzi, G. Falauto, and M. Sykora, JIST: Just-In-Time scheduling translation for parallel processors, Scientific Programming, 2005.

L. Michel, N. Fournel, and F. Pétrot, Fast simulation of systems embedding VLIW processors, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '12, 2012.
DOI : 10.1145/2380445.2380472

URL : https://hal.archives-ouvertes.fr/hal-00815815