Embedded systems are being increasingly network interconnected. They require to interact with their environment through text-based protocol messages. Parsing such messages is control-dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated to an automated design methodology that enables a SoC/SoPC system generation from high-level specifications of message protocols. Experimental results obtained on a Xilinx ML605 board show acceleration factors ranging from 4 to 11. Both static and dynamic reconfigurations of coprocessors are discussed then evaluated so as to reduce the system hardware complexity.