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Communication Dans Un Congrès Année : 2015

On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks

Backer Jerry
  • Fonction : Auteur
Ramesh Karri
  • Fonction : Auteur

Résumé

The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without modifying IP cores. We add hardware components to configure the debug architecture for security monitoring, to store a golden software execution model, and to notify a trusted kernel process when an attack is detected. Our evaluations show that the additions do not impact runtime software execution, and incur 9% area and power overheads on a low-cost processor core.
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Dates et versions

hal-01398767 , version 1 (17-11-2016)

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Citer

Backer Jerry, David Hely, Ramesh Karri. On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on, IEEE, Oct 2015, Amherst, United States. ⟨10.1109/DFT.2015.7315131⟩. ⟨hal-01398767⟩

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