Modelling and synthesis of optimal adders under left-to-right input arrival
Résumé
In this paper parallel adders with minimum delay and minimum complexity under left-to-right sequential input arrival are investigated. The delay is the result time after the arrival of the last input digits which are the least significant ones. An analytical model of the complexity is established and a synthesis algorithm is described. The algorithm is implemented on a powerful multiview layout synthesis tool called GenOptim. This CAD tool outputs a set of different descriptions including: a netlist view, a layout view, a VHDL behaviour view and finally a test view including functional and structural test patterns with a very high fault coverage.
