Smart Power integrated circuits receive an increasing attraction recently, especially in automotive industry. Sub-strate noise coupling is one of the major causes of failure in this kind of integrated circuits that requires circuit redesign and increases the overall cost. An exhaustive failure analysis is needed to identify failures due to substrate coupling. In this paper, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. Based on this methodology, we have developed a dedicated Computer-Aided-Design tool that is used for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate parasitic generation. To validate the substrate model, the process of benchmarking uses industrial design structures in 0.35µm high-voltage-CMOS technology. Two test cases in transient simulation are considered in this work. The first one is a common used current mirror circuit. Our tool predicts the interference of substrate currents to this basic circuit. The second test case is an industrial design test-chip where parasitic coupling is investigated in a standard automotive test. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noise at early phase before fabrication.