Laser attacks are an effective threat against secure integrated circuits, due to their capability to inject very precise hardware faults. Evaluation of such attacks at RTL provides to designers the means to increase the security level of an IC, during the design stage and without the need to perform multiple design re-spins. An RTL laser fault model that attempts to model the locality of laser attacks, early in the design flow, has already been proposed in the literature. The current work presents detailed results on the validation of the RTL laser model, with respect to layout information for multiple designs. Furthermore we perform a statistical analysis on the RTL predictions, in order to calculate the percentage of the generated fault space that actually corresponds to local faults according to layout information.