Secured Structures for Secured Asynchronous QDI Circuits
Résumé
This paper aims at introducing a novel design methodology of compact, high performance and secured dual rail primitives widely used in quasi-delay insensitive circuits. An example of application of this design methodology to basic QDI primitives is given on a 130nm process. The performance and the security properties of the resulting cells are then compared, using electrical simulations, to the implementations proposed in former works.