Pre-sorted Forward-Backward NB-LDPC Check Node Architecture
Résumé
This paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced pre-sorting technique to the forward-backward architecture. The pre-sorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees).
Domaines
Electronique| Origine | Fichiers produits par l'(les) auteur(s) |
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