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Communication Dans Un Congrès Année : 2016

Ultra-Low Power Frequency Synthesizer Based on a Dual-Locking Ring Oscillator

Résumé

An ultra-low power frequency synthesizer based on a 28-nm CMOS dual-voltage controlled ring oscillator is presented. The technological dispersion and temperature effects are tackled thanks to a Delay locked loop (DLL) which sets a coarse tuning voltage. A back-gate fine tuning voltage is used to lock the oscillating signal on a pure reference with a Phase locked loop (PLL). The close-in intrinsically-poor phase noise of the ring oscillator is cleaned up by the PLL. The overall system consumes less than 100µW to generate a 2.5GHz signal.
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Dates et versions

hal-01377960 , version 1 (08-10-2016)

Identifiants

  • HAL Id : hal-01377960 , version 1

Citer

Yann Deval, Yoan Veyrac, François Rivet. Ultra-Low Power Frequency Synthesizer Based on a Dual-Locking Ring Oscillator. 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct 2016, Hangzhou, China. ⟨hal-01377960⟩
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