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Communication Dans Un Congrès Année : 2005

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation

Résumé

We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%.
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Dates et versions

hal-01372839 , version 1 (27-09-2016)

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Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Sep 2005, Puebla City, Mexico. pp.21-25, ⟨10.1109/RECONFIG.2005.23⟩. ⟨hal-01372839⟩
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