Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA - Archive ouverte HAL Access content directly
Conference Papers Year : 2010

Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA

Abstract

The Wave Dynamic Differential Logic (WDDL) offers an affective way to address Differential Power Attack (DPA). However, the effectiveness of this countermeasure is guaranteed provided the routing of both the real and complementary paths is balanced, to obtain equal propagation delays and power consumption on differential signals.
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hal-01372837 , version 1 (27-09-2016)

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Emna Amouri, Zied Marrakchi, Habib Mehrez. Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Dec 2010, Kuala Lumpur, Malaysia. pp.296--299, ⟨10.1109/APCCAS.2010.5774878⟩. ⟨hal-01372837⟩
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