The miniaturisation of integrated circuits leads to reliability issues such as electromigration (EMG). This well-known phenomenon is checked at design level by CAD tools. The conventional EMG check methods are based on electrical parameters. However, the wire physical degradation depends also on the interconnection network structure. In order to improve the EMG check methodologies, we propose an accurate method based on failure mechanism and chip power grid configuration. Indeed, the power grid offers redundant paths in case of void in main power supply path. The principle of our method is to take into account the contribution of these redundant paths in power grid lifetime assessment. These effects are validated by silicon ageing tests on structures designed in 28 nm Full Depleted Silicon on Insulator (FDSOI). These accelerated tests results have confirmed the lifetime gain due to the redundancy. These results provide perspectives for the relaxation of wire current limits and improve the chip design toward EMG.