As the flexibility offered by fine-grained field programmable gate array (FPGA) comes at a significant cost of area, speed, and power, there is a trend to use coarse-grained architecture (CGA) for dataflow applications requiring high computational resources. Existing CGA solutions are characterized according to the general organization, the processing element architecture, the basic interconnect structure and their reconfiguration characteristics. Based on the study of several digital signal processing (DSP) applications and their implemented VLSI architectures, we propose a CGA with parameterizable and flexible blocks based on a generic matrix and interconnected by a configurable network. The proposed architecture provides a good tradeoff between flexibility and performance-density. A CAD tool is developed to automate the implementation of the design on the architecture. A synthesizable VHDL code generator is also developed in order to further explore and validate the proposed architecture. The unification of coarse-grained logic block and bus-based interconnection bridges the gap between application-specific integrated circuit (ASIC) and CGA, resulting in area reduction from 40× to 6×, respectively. Experimental results demonstrate the performance and efficiency of the proposed architecture to implement DSP designs.