Substrate noise coupling due to minority carriers propagation in smart power integrated circuit becomes a critical issue specially for high voltage applications. Computer-Aided-Design modeling methodology for substrate parasitic-immune design was introduced. It is based on constructing a 3D substrate equivalent network. The substrate equivalent network consists of models of diodes and resistors that are capable of preserving the continuity of minority carriers. In this paper, an optimized meshing topology for substrate modeling is introduced. This meshing topology contributes significantly in the extracted component reduction and hence speeds up the simulation while improving the convergence of the simulator. A typical NPN bipolar transistor is used as case study. Comparing the proposed meshing topology to the basic meshing topology, the number of extracted components is reduced by 78% and the simulation time is lowered by 88%. SPICE-like analysis results confirm the accuracy of modeling approach with an acceptable relevant error (<10%) compared to standard model. With the proposed meshing topology, it is feasible to model the substrate parasitic of more complex smart power integrated circuit.