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            <title xml:lang="en">A Low-Voltage CMOS Buffer for RF Applications Based on a Fully-Differential Voltage-Combiner</title>
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                <forename type="first">S.</forename>
                <surname>Abdollahvand</surname>
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            <idno type="halRefHtml">&lt;i&gt;4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS)&lt;/i&gt;, Apr 2013, Costa de Caparica, Portugal. pp.611-618, &lt;a target="_blank" href="https://dx.doi.org/10.1007/978-3-642-37291-9_66"&gt;&amp;#x27E8;10.1007/978-3-642-37291-9_66&amp;#x27E9;&lt;/a&gt;</idno>
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                <title xml:lang="en">A Low-Voltage CMOS Buffer for RF Applications Based on a Fully-Differential Voltage-Combiner</title>
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                <editor>Luis M. Camarinha-Matos</editor>
                <editor>Slavisa Tomic</editor>
                <editor>Paula Graça</editor>
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                <term xml:lang="en">low-voltage</term>
                <term xml:lang="en">CMOS</term>
                <term xml:lang="en">RF</term>
                <term xml:lang="en">common-drain</term>
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              <p>This paper presents a new CMOS buffer circuit topology for radio-frequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source degeneration technique is used. The proposed circuit has been designed in a 130nm logic CMOS technology and it achieves a simulated gain of 1.54 dB, a bandwidth of 1.14 GHz for a total power dissipation of 13.34 mW, when driving an RF active probe (with 0.8 pF in parallel with 200 kΩ).</p>
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