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Communication Dans Un Congrès Année : 2013

Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel

Frederico Rocha
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Ricardo Martins
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Nuno Lourenço
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Nuno Horta
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Résumé

This paper applies to the scientific area of electronic design automation (EDA) and addresses the automatic sizing of analog integrated circuits (ICs). Particularly, this work presents an innovative approach to enhance a state-of-the-art layout-aware circuit-level optimizer (GENOM-POF), by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint optimization kernel based on the NSGA-II algorithm. The approach was validated with typical analog circuit structures, using the UMC 0.13 μm integration technology, showing that, by enhancing the circuit sizing optimization kernel with the gradient model, the optimal solutions are achieved, considerably, faster and with identical or superior accuracy. Finally, the results are Pareto Optimal Fronts (POFs), which consist of a set of fully compliant sizing solutions, allowing the designer to explore the different trade-offs of the solution space, both through the achieved device sizes, or the respective layout solutions.
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hal-01348799 , version 1 (25-07-2016)

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Frederico Rocha, Ricardo Martins, Nuno Lourenço, Nuno Horta. Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel. 4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2013, Costa de Caparica, Portugal. pp.531-538, ⟨10.1007/978-3-642-37291-9_57⟩. ⟨hal-01348799⟩
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