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Communication Dans Un Congrès Année : 2016

A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)

Résumé

The incoming communication standards (e.g. 5G, cognitive radio, SDR...) will be the origins of a deep revolution for the future of our widely connected world, with new communication scenarios, communications interoperability (e.g. wireless broadband, Internet of Things, Machine to Machine, Smart&Digital Factory...). As an example, contrary to 3G or 4G, the incoming 5G standard gathers several different radio signals (LTE-A, Wi-Fi/WISE…) in licensed or free bandwidth, in a combined heterogeneous and flexible network; also, in the defence and security domain, the advent of the Software Defined Radio (SDR) follows the operational logic of interoperability and cost-reductions to rationalise stocks of radio equipments, by implementing various waveforms on the same telecommunication equipment... This trend will be characterized by convergence of communication networks, melting several physical layers, several communication protocols (Wi-Fi, LTE, RFID tags...). This supposes to deal with several different channel codes, different consumption constraints, throughput targets...; in other words, this future world will be based on multiple radio (multi-RAT), allowing a dynamic adaptation in frequency, codes... and heterogeneous networks. In this context, channel decoding (i.e. FEC, Forward Error Correction) architecture is a critical element of such systems, since it impacts the quality of services (QoS), power consumption and the efficiency of radio resources usage. In order to limit the costs, either in terms of development cost or power consumption cost, an adaptive architecture that could deal with some (or all) of these applications/codes is extremely interesting. It also requires to be extensible (various throughput/latency targets) and flexible ECC architectures, i.e. supporting of several types of codes (turbo codes, LDPC, polar codes...) that can be changed dynamically during operation. However, the excellent performance of current FEC decoders comes at the expense of huge computational complexity. Hence, parallel architectures must be employed to speed up the decoding process and support required application throughputs. Moreover, several parameters such as scheduling, parallelism level, memory organization and network architecture need to be explored to tradeoff circuit area and performances. This requires the development of dedicated approaches to efficiently implement decoder architecture. In such implementation several Processing Elements (PEs) are used to obtain the required throughput. Memories are used to store different messages generated during the decoding process. These messages are written into and read out of the memories according to particular permutation defined by a permutation law. In order, to propose FEC decoder architectures that could meet the previous requirements, new architectural technologies must be explored. This contribution presents an innovative approach to design efficient, low-power, agile and dynamically reconfigurable ECC (Error Correction Codes) architectures in order to reduce the hardware cost and to support multiple standards with reduced memory footprint. In other words, our goal is to propose a single architecture that could be used to deal with all 5G communications and/or SDR and/or … for a minimized specialization overhead (hopefully for free). One of the problems, for example, is that such architectures suffer from memory access conflicts due to concurrent data accesses (from PEs to memories). This issue comes from the interleaving law in turbo-like codes or from the parity check matrix in LDPC. Different approaches have been developed to tackle this problem: definition of conflict-free data access orders, using dedicated hardware mechanisms to deal with conflicts at runtime, finding conflict free memory mappings at design time (off-chip) or more recently hybrid strategy that finds conflict free memory mappings on-chip at runtime. In parallel decoder architectures, design time approaches require storing into ROM the control words to drive the network and to address data memories for particular block length or/and interleaving law. So, in order to design flexible decoder architectures that support multiple block lengths and interleaving laws, multiple ROMs are needed which results in an important hardware overhead. Our proposed architecture is based on the implementation of a patented approach for FEC hardware architecture. Currently, it is clear that latency required to implement our algorithm is in compliance of existing telecommunication standards (4G LTE). However, the low architectural cost of our algorithm makes it suitable to embed on telecommunication and signal processing system for supporting multiple applications and standards (i.e. like in 5G, Cognitive Radio…).
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Dates et versions

hal-01344550 , version 1 (12-07-2016)

Identifiants

  • HAL Id : hal-01344550 , version 1

Citer

Cyrille Chavet, Philippe Coussy. A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond). WInnComm Europe, Oct 2016, Paris, France. ⟨hal-01344550⟩
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