Software-based test of SoCs consists in testing IP cores using embedded processor cores. Previously proposed solutions are usually ad-hoc. Therefore, this paper presents STESOC, a software-based Test Access Mechanism for SoCs containing standard-wrapped IP cores. Under the control of the embedded microprocessor, a dedicated test-coprocessor tests the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESOC architecture and a classical bus-based strategy.