High performance, low cost, and double node upset tolerant latch design
Résumé
In this paper, a high performance, low cost, and double-node-upset (DNU) tolerant latch design (referred to as HLDUT) is proposed in 22nm CMOS technology. The latch mainly consists of a single-node-upset (SNU) resilient cell and a 3-input C-element, and the SNU resilient cell mainly constructs from triple mutual feedback 2-input C-elements, thus the latch is DNU (let alone SNU) tolerant. Using clock gating methodology, high speed transmission path, and fewer transistors, the latch also performs with lower overheads regarding power dissipation, transmission delay, and silicon area. Simulation results have demonstrated the SNU/DNU tolerability, and a ~97.44% area-power-delay product saving for the latch design on average compared with the previous radiation hardened latch designs.
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