Low latency combination of parallelized single-pass LVCSR systems - Archive ouverte HAL Access content directly
Conference Papers Year : 2012

Low latency combination of parallelized single-pass LVCSR systems

(1, 2) , (2) , (2) , (1)
1
2

Abstract

Recent progress in hardware technology, especially multi-core CPUs, offer new perspectives to accelerate software by parallelizing the computing process. But, it is still considered as a difficult task to parallelize the execution of an ASR system, as the different steps are usually sequential. This paper addresses some opportunities offered by parallelism for ASR system combination: the proposed approach consists in making on the fly combination , whereas the classical approach consists in only combining final outputs. This approach is particularly relevant for applications which need a very low latency response. This paper presents some preliminary results which show a 14% relative reduction in Word Error Rate with a limited impact on the latency due to ASR system combination. Index Terms: LVCSR system harnessing, driven decoding , local ROVER combination.
Not file

Dates and versions

hal-01313238 , version 1 (09-05-2016)

Identifiers

  • HAL Id : hal-01313238 , version 1

Cite

Fethi Bougares, Mickael Rouvier, Yannick Estève, Georges Linarès. Low latency combination of parallelized single-pass LVCSR systems. Interspeech, Sep 2012, Portland, United States. ⟨hal-01313238⟩
119 View
0 Download

Share

Gmail Facebook Twitter LinkedIn More