This paper presents a systematic comparison between two different implementations of a distributed network on chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized multi processors system on chip. The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.