Laser attacks are an effective threat against secure integrated circuits, due to their capability to inject very precise hardware faults. Evaluating the effect of such attacks from RTL descriptions provides designers a means to increase the security level of an IC, early in the design stage and without the need to perform multiple design re-spins. An RTL laser fault model that attempts to model the locality of laser attacks, early in the design flow, has already been proposed in our previous works. The current work presents detailed results on the validation of this model, with respect to layout information for multiple designs. Furthermore we perform a statistical analysis on the RTL predictions, in order to calculate the percentage of the fault space generated using only RTL information that actually corresponds to local faults according to layout information.