Automatic Layout Generator of Domain Specific FPGA: - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2008

Automatic Layout Generator of Domain Specific FPGA:

Résumé

This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of single event upsets (SEU). The FPGA layout is generated in a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated and taped out in 130 nm technology.
Fichier non déposé

Dates et versions

hal-01299216 , version 1 (07-04-2016)

Identifiants

Citer

Hayder Mrabet, Husain Parvez, Zied Marrakchi, Habib Mehrez. Automatic Layout Generator of Domain Specific FPGA:. ICM International Conference on Microelectronics, Dec 2008, Sharjah, United Arab Emirates. pp.183-186, ⟨10.1109/ICM.2008.5393493⟩. ⟨hal-01299216⟩
73 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More