Embedded coarse-grained blocks are becoming increasingly popular in advanced field programmable gate arrays (FPGAs) devices to improve their performance. In this paper a Tree-based coarse-grained FPGA architecture is proposed and it is then compared with VPR-style [1] Mesh-based coarse-grained architecture. Tree-based architecture is a multilevel hierarchical architecture that comprises two unidirectional interconnects whereas Mesh-based architecture is column based that uses unidirectional routing. Both architectures can support different kinds of coarse-grained blocks that are defined using architecture description files. For the evaluation of two architectures, separate software flows are developed for both the architectures that have resulted in the successful placement and routing of various digital signal processing (DSP) benchmarks. Area comparison, based on the results obtained after the placement and routing of these DSP benchmarks, reveals an average area gain of 27% for Tree-based architecture over Mesh-based architecture.