It has been shown in previous works that non-uniform sampling and processing is a better scheme than the uniform sampling to sample and process low activity signals. Non-uniform sampling technique generates fewer samples, which means less data to process and lower power consumption. Furthermore, asynchronous logic is known to be data-driven. It proves to be more adapted to the non-uniform sampling than synchronous logic. It is thus a better alternative to design low power data-processing circuits. In this paper, we present an overview of the non-uniform sampling scheme. It also describes the architectures of a processing function (Finite Impulse Response filter) in synchronous and asynchronous technologies. These circuits have been implemented on an Altera EP2C8 FPGA in order to extract and compare their activities profiles.