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A Clock-less 8-bit folding A/D converter


This paper presents a continuous-time 8-bit folding analog-to-digital converter. The clock-less architecture is composed of 8 identical stages with 1 bit/stage. The circuit is designed in a 350nm CMOS process with a supply voltage of 3.3V. Simulation results show that the 8-bit clock-less ADC can achieve a Signal-to-Noise and Distortion Ratio of 53dB. The ADC has a power consumption of 5.51mW. The proposed circuit is compared with a similar continuous-time 8-bit pipeline ADC with 1 bit/stage.
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hal-01292488 , version 1 (23-03-2016)



Sabiniano A. Rodrigues, Hassan Aboushady, Marie-Minerve Louërat, José I. C. Accioly, Raimundo C. S. Freire. A Clock-less 8-bit folding A/D converter. IEEE Latin American Symposium on Circuits and Systems (LASCAS), Feb 2010, Foz do Iguacu, Brazil. pp.25-28, ⟨10.1109/LASCAS.2010.7410131⟩. ⟨hal-01292488⟩
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