The particular form of the task graph of many telecommunication applications permits a high level of coarse grained parallelism. We consider a classification application on a telecommunication oriented multiprocessor system-on-chip (MP-SoC) platform. The hardware architecture hosting this type of application contains many programmable processors and dedicated hardware coprocessors, sharing the same address space. Inter-task communications are implemented via Multi-Writer Multi-Reader (MWMR) channels placed in shared-memory. To meet the strict requirements of this type of application, several performance bottlenecks have to be overcome. We show how our tool DSX (Design Space Explorer) helps to analyze these bottlenecks and outline the perspectives for further improvement.