An application specific FPGA (ASIF) is an FPGA with reduced flexibility and improved density. A heterogeneous ASIF is reduced from a heterogeneous FPGA for a predefined set of applications. This work presents a new tree-based heterogeneous ASIF and uses two sets of open core benchmarks to explore the effect of lookup table (LUT) and arity size on it. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results. However, smaller LUTs produce worse results in terms of delay. Further experimental results show that for tree-based ASIF, the combination LUT 4 with arity 16 for SET I and LUT 3 with arity 16 for SET II gives best results in terms of area-delay product. Area comparison between mesh and tree-based ASIFs shows that tree-based ASIF gives 11.27% routing area gain for SET I and gives almost same area results for SET II while consuming 70.30% and 69.80% less wires for SET I and SET II benchmarks respectively. Finally the quality analysis shows that tree-based ASIF produces around 18% better results compared to mesh-based ASIF.