This paper presents a background time skew calibration technique for time-interleaved analog-to-digital converter (TIADC). It depends on the phase detection between a digitally generated calibration signal and the output of each ADC in the system that suffers from time skew mismatch. Digitally controlled delay lines (DCDL) are used to minimize the time skew mismatches among the clock routes. The calibration technique behaviors are theoretically analysed and verified by simulations. 12-bit 4-channel, 800 MSps TIADC is used as an example