—The growing complexity of current and future wireless communication systems makes power estimation a challenging task for designers. Nowadays, it is required to estimate power very fast in order to explore and validate design choices as soon as possible in the design flow. In this paper, we propose a new dynamic power estimation methodology for FPGA-based systems. Our methodology aims to provide accurate and fast power estimations of an entire system prior to any implementation. It also aims at making design space exploration easier. We introduce a scenario-level in order to facilitate the comparison of domain-specific algorithms. This methodology relies on an IP power characterisation phase and a behavioural simulation of the modeled system using SystemC. We show the effectiveness of our approach on typical wireless communication systems which leads to a maximum absolute error lower than 6% compared to classic estimations.