In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. Electrical noise induced by power stage switching or external disturbances generates parasitic substrate currents, leading to a local shift of the substrate potential which can severely disturb low voltage circuits. Nowadays this is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an on-chip noise sensor dedicated to measurements of transient voltage fluctuations induced by high voltage activity and coupled by the substrate.