This chapter presents a designer-assisted analog synthesis flow that is fully controlled by the designer and offers an intuitive design approach. The designer knowledge to conceive an analog IP is the key element of the synthesis flow, it is taken into account to automatically generate the analog IP design procedure and the physical view. Thus both consistency and accuracy of the final design are ensured. The presented flow bridges the gap between the two traditional approaches related to analog synthesis, namely the simulation-based and the knowledge-based approaches. It combines accuracy from simulation-based approaches with speed of computation from knowledge-based approaches. The proposed analog synthesis flow is composed of an accurate hierarchical sizing and biasing tool and a parameterizable layout generation tool. To demonstrate the effectiveness of the proposed flow, a fully differential transconductor was completely synthesized in 130nm CMOS technology to respect some performance specifications set by the designer. The obtained very low runtime is due to the introduction of design knowledge during both sizing and layout generation.