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Communication Dans Un Congrès Année : 2015

Design of analog subthreshold encoded neural network circuit in sub-100nm CMOS

Résumé

Encoded Neural Networks (ENN) associate lowcomplexity algorithm with a storage capacity much larger than Hopfield Neural Networks' (HNN) for the same number of nodes. They are thus promising for implementing large scale neural networks mimicking the functioning of the human brain. The implementation of such network on chip requires reducing the power consumption of the nodes to the femtojoule range to compare to human brain figures. Moreover, the circuit area must be reduced as much as possible. To address these challenges, this paper proposes a subthreshold analog ENN designed for the ST 65nm CMOS process. The designed circuit accepts power supply between 0.3V and 0.86V with currents below 300nA, yielding a 32fJ energy consumption per decoding per node. The ENN converges only 21ns after being stimulated. Finally, the node has a surface area of only 9.5µm^2
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Dates et versions

hal-01217841 , version 1 (20-10-2015)

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Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel. Design of analog subthreshold encoded neural network circuit in sub-100nm CMOS. IJCNN 2015 : IEEE International Joint Conference on Neural Networks, Jul 2015, Killarney, Ireland. pp.1 - 7, ⟨10.1109/IJCNN.2015.7280672⟩. ⟨hal-01217841⟩
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