Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions - Archive ouverte HAL Access content directly
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Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions

Ronan Lucas
  • Function : Author
Emmanuel Vaumorin
  • Function : Author
Philippe Cuenot
  • Function : Author
Yao Li
  • Function : Author
  • PersonId : 969945
Zhi Wang
  • Function : Author
  • PersonId : 970067
Jean-Paul Chaput
  • Function : Author
  • PersonId : 970066
Martin Barnasconi
  • Function : Author
Thilo Vörtler
  • Function : Author
Karsten Einwich
  • Function : Author

Abstract

This paper will present a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT. The UVM foundation elements such as test, environment, UVC (Universal Verification Component), transactions and associated configuration objects are introduced, which are packaged by means of IP-XACT vendor extensions. The benefit is to facilitate the (re)use of UVM components and environments by providing a readable and configurable test platform description, to trace the requirements of tests, and to generate automatically the entire UVM environment and simulation build flow after configuration of the test scenario. The automation technology is based on IP-XACT and uses new capabilities of the Magillem tools solution.
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Dates and versions

hal-01217214 , version 1 (19-10-2015)

Identifiers

  • HAL Id : hal-01217214 , version 1

Cite

Ronan Lucas, Emmanuel Vaumorin, Philippe Cuenot, Yao Li, Zhi Wang, et al.. Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions. Design and Verification Conference and Exhibition (DVCON Europe), Oct 2014, Munich, Germany. ⟨hal-01217214⟩
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