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Communication Dans Un Congrès Année : 2015

A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing

Résumé

—Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. In this paper a new hardware aware check node algorithm and its architecture is proposed. It has state-of-the-art communications performance while reducing the decoding complexity. The presented architecture has a 14 times higher area efficiency, increases the energy efficiency by factor 2.5 and reduces the latency by factor of 3.5 compared to a state-of-the-art architecture.

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Domaines

Electronique
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Dates et versions

hal-01216603 , version 1 (16-10-2015)

Identifiants

  • HAL Id : hal-01216603 , version 1

Citer

P Schläfer, V Rybalkin, N Wehn, M Alles, T Lehnigk-Emden, et al.. A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing. IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC) 2015, Aug 2015, Hong-Honk, France. ⟨hal-01216603⟩
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