Bit Plane coding constitutes an important component of the Hierarchical Enumerative Coding (HENUC). This paper proposes a novel multithreaded processing paradigm for parallel bit plane coding that achieves near perfect parallel processing scalability, at least over the 4 logical processors. It is a very high speed and efficient structure that is capable of encoding all bits of the wavelet coefficient in only one scan, and largely decreases the memory requirement; Experimental results show that the architecture can encode about 5 times more than the sequential encoding for the coefficient with 8 bits and it requires %30 bits memory less than the basis solution.