In this paper, we introduce a modeling methodology for field bus-based embedded systems that allows dynamic evaluation of their signal integrity characteristics at the virtual prototyping step. Our methodology is based on the following criteria: 1) a signal integrity-aware I/O interface mixed model; 2) a physical model of transmission lines to estimate signal degradation caused by the bus lines; and 3) an ICEM model to estimate the impact of a chip's internal activity on its power voltage or its I/O. Through simulations and experimental validations, we show that our methodology allows functional validation of the design and can also evaluate some low-level effects such as the influence of an embedded software instruction on the voltage drops in the power rails.