A PCI compliant three-state input/output buffer featuring low power consumption, absence of passive elements and easy mapping on different target processes is presented. Firstly, a portable approach to layout using a process independent unit, named λ, that allows - in first approximation - to scale the design is introduced. Secondly, the PCI requirements and outline the main constraint for CMOS pads design are presented, that is, minimum fan-out and maximum slew rate are incompatible using a classical buffer. This leads to the definition of a buffer being where driving power and output slew rate are controlled independently. A full transistor scheme is presented and it is shown how to reach the PCI specifications using appropriate sizes for the transistors. It turns out that a power vs delay trade-off can be done by modifying a few transistor widths. Compliance is obtained using the same λ layout for two 0.8 μm and two 0.5 μm technologies.