In this paper, we investigate the most appropriate ADC for an array of probe storage devices. Power consumption and area are crucial in this application, since one ADC is associated with each read channel. The read-channel specifications of the probe storage device require an ADC with seven bits of resolution at a rate of 100 kSample/s. Five different ADC architectures have been implemented for the desired specifications: a first- and a second order discrete-time $\Sigma \Delta$, a second order continuous-time $\Sigma \Delta$ and a cyclic ADC. The system and circuit design methods of each architecture are presented. The different architectures are compared based on the measurement results of the five fabricated circuits.