Based on non-uniform sampling techniques and event-driven logic, signal processing is evolving to integrate new demands such as power consumption. As power is mainly connected to the processing activity and data volume, the level-crossing sampling scheme offers a simple way to reduce data volume and consequently processing activity. Nevertheless, these good properties could be constraining for the designers because of the non-predictable sample number that can be involved in the processing. In this paper, we target a FIR filter architecture and show how to correctly size its input shift-register. This paper shows a strategy to choose the shift-register depth but also a way to dynamically adapt the computation to an heterogeneous data flow.