Early performance evaluation of embedded systems extensively uses discrete-event simulation of high level architecture models. Due to increasing complexity of system architectures, simulation speed needs to be improved to guarantee evaluation of candidate architectures in acceptable time. In this paper, we introduce a timing correction technique that allows the number of processes managed by the simulation kernel to be reduced. The presented technique uses knowledge about application and platform to preserve accurate simulation results in case of contention at shared resources. We have implemented this simulation technique into an industrial modeling framework. Our experiments show that a simulation speed-up by a factor of 7 can be achieved with no loss of accuracy. The proposed approach has thus potential to improve the evaluation process of architectures.