Failure Analysis of ESD-stressed SiC MESFET
Résumé
Reliability studies are required for SiC device development. In a previous work we studied the intrinsic
ESD robustness of a SiC MESFET. The failure mechanism was related to the triggering of an NPN parasitic
transistor. In this work, a new MESFET layout is considered, which optionally include a Zener diode for internal
protection. TLP testing and failure analysis has been carried out. Two new failure mechanisms are evidenced.
Based on this knowledge, solutions are proposed to further improve the ESD robustness.
Domaines
Electronique| Origine | Fichiers produits par l'(les) auteur(s) |
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