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Article Dans Une Revue Microelectronics Reliability Année : 2015

Failure Analysis of ESD-stressed SiC MESFET

Résumé

Reliability studies are required for SiC device development. In a previous work we studied the intrinsic ESD robustness of a SiC MESFET. The failure mechanism was related to the triggering of an NPN parasitic transistor. In this work, a new MESFET layout is considered, which optionally include a Zener diode for internal protection. TLP testing and failure analysis has been carried out. Two new failure mechanisms are evidenced. Based on this knowledge, solutions are proposed to further improve the ESD robustness.

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Electronique
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Dates et versions

hal-01176674 , version 1 (17-07-2015)

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Tanguy Phulpin, David Trémouilles, Karine Isoird, Dominique Tournier, Philippe Godignon, et al.. Failure Analysis of ESD-stressed SiC MESFET. Microelectronics Reliability, 2015, 55 (9-10), pp.1542-1548. ⟨10.1016/j.microrel.2015.06.121⟩. ⟨hal-01176674⟩
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