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Article Dans Une Revue Microprocessors and Microsystems: Embedded Hardware Design Année : 2015

P2IP: A novel low-latency Programmable Pipeline Image Processor

Résumé

This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P 2 IP. The P 2 IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurabil-ity of the P 2 IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P 2 IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P 2 IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications.
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Dates et versions

hal-01171651 , version 1 (06-07-2015)

Identifiants

Citer

Paulo Possa, Naim Harb, Eva Dokladalova, Carlos Valderrama. P2IP: A novel low-latency Programmable Pipeline Image Processor. Microprocessors and Microsystems: Embedded Hardware Design , 2015, In press. ⟨10.1016/j.micpro.2015.06.010⟩. ⟨hal-01171651⟩
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