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Communication Dans Un Congrès Année : 2014

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

Baudouin Martineau
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V. Knopik
  • Fonction : Auteur
Didier Belot
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  • PersonId : 841239

Résumé

A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (PSAT) of 19.9 dBm and a 1-dB compressed output power (P-1dB) of 17.2 dBm while achieving maximum power added efficiency (PAEmax) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm2. To the author's knowledge, this amplifier presents the highest figure of merit (FOM ITRS) among 60 GHz PAs using silicon technology.

Domaines

Electronique
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Dates et versions

hal-01110611 , version 1 (28-01-2015)

Identifiants

  • HAL Id : hal-01110611 , version 1

Citer

Aurélien Larie, Eric Kerherve, Baudouin Martineau, V. Knopik, Didier Belot. A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS. ESSCIRC 2014, Sep 2014, VENISE, Italy. pp.175-178. ⟨hal-01110611⟩
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