CMOS fully integrated reconfigurable power amplifier with efficiency enhancement for LTE applications
Résumé
A fully integrated power amplifier (PA) using power cell switching (PCS) technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers (DATs) are used as splitter, combiner and DC bias feed to partition the power requirements among the parallelized power cells. Individual cell can be dynamically turned ON/OFF according to the desired output power. At 2.5GHz, measured maximum output power is 28.2dBm and PAE is improved for low level, +3.2% and +4.9% for 18dBm and 23.7dBm respectively