This article gives a survey on formal hardware verification tools developed in Europe. It describes the main objectives and domains of application of the formal methods for the verification of electronic system-on-a-chip models and designs. Further, it attempts to introduce some classification scheme for the existing commercial or prototype tools, which is based on the different verification aspects: proof technique, type of the circuit, abstraction level, verification objective, mathematical model, input format, diagnostic method incorporated, verification execution and shows the particular results for each of these aspects. Finally, some conclusions concerning the possible future trends in development are drawn.